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BMW Lane Departure
The Wall Street Journal Features Mobileye: 'A Warning System as Your Co-Pilot'
Wall Street Journal, June 2007
Mobileye N.V. and Yazaki Corp. Sign Agreement for Distribution in Japan of the AWS-3000
June, 2007
GM Announces 2008 Cadillac STS to Include Mobileye's LDW Technology
May 2007
Siemens VDO and Mobileye N.V. Supply Lane Departure Warning to BMW’s 5 Series
March 2007
Manufacturer Products Processing Platforms EyeQ

EyeQ™, Mobileye's System-on-Chip (SoC) delivers a solution for computationally intensive applications for real-time visual recognition and scene interpretation and has cabin-grade automotive qualification for use in intelligent vehicle systems.
EyeQ™ is to be launched in 2007 start of production on four different major US and European platforms covering applications of lane departure warning (LDW) and LDW with Vehicle Detection with fusion (active braking).
The EyeQ™ is also in production for the Mobileye's Advance Warning System (AWS).
EyeQ™ is manufactured by STMicroelectronics.
The chip architecture is designed to run a full-fledged application on a single chip, and is completely programmable to accommodate a wide range of visual processing applications beyond automotive specific applications.  EyeQ™ is manufactured using the leading CMOS 0.18-micron technology, operating at 120Mhz. To optimize cost performance, all peripheral interfaces are integrated in to the SoC, including dual CAN Controllers; a UART, SDRAM controller, parallel I/O, and Video image data capture units.
EyeQ™ is an ultra low cost device but with the theoretical equivalent computation power of an Intel Pentium IV processor, running at 4Ghz clock rate.
The EyeQ™ architecture consists of two 32 bit RISC ARM946E CPUs, four Vision Computing Engines (VCE), a multi channel DMA and several peripherals. The ARM946E Control CPU manages the four VCEs, the ARM946E Logic and the multi-channel DMA as well as the other Peripherals. The four VCEs and the ARM946E Logic perform all the intensive vision computations required by the applications such as tracking and pattern classification.
The Multi-Layer 4x4 Matrix offers a high connectivity scheme that is needed for providing the required data bandwidth of the vision processing. The Multi-Layer matrix routes the four master ports to the four slave ports and enables concurrent operation of up to four AHB buses. If there is a bus contention on a slave port, the Multi-Layer AHB matrix decides on the winning AHB master according to the priority scheme.
All the VCEs work in parallel, retrieving their tasks from tasks queues (one per each VCE). The VCEs communicate over the high bandwidth Multi-Layer Matrix block, via a common master port.  The task queues are managed by the ARM9E Control CPU. A high-speed, 64bit width, 288Kbyte on-chip SRAM is located on this Multi-Layer Matrix for fast image memory storage and retrieval.
A separate 32-bit low bandwidth Peripheral Bus (VPB) is provided to connect all of the various peripherals such as the CAN Controllers.
Vision Computing Engines (VCEs) 
EyeQ™ has four hardware modules optimized for computing of the major time-consuming image processing tasks. The VCE modules are:
Classifier Engine:
Image scaling & preprocessing
Image pattern classifier
Tracker Engine:
Image warping
Image tracking
Lane Detection Engine:
Lane markings detection
Road Geometry detection

Site Map Window, Preprocessing and Filter (WPF) Engine:
Image convolver
Image pyramid creation
Edge detection
Image filters
Image histogram

DMA Controller:
The eight channels DMA Controller is located on Master Port #4 of the multi Layer Matrix bus. The DMA Controller is programmed by the ARM9 Control CPU to support the captured video stream via the Video Interfaces block and for on and off chip general data transactions. Main features are:
Memory to memory, Peripheral to memory, and peripheral to peripheral transfers
Up to 16 peripheral DMA requests
8 DMA channels, each channel can support a unidirectional transfer
Scatter or Gather DMA is supported through the use of linked lists
Two AHB masters for transferring data
32bit AHB bus width
Multi Layer 4x4 Matrix 
The Multi Layer 4x4 Matrix enables a high connectivity scheme that is required to provide the data bandwidth of the vision processing:
64bit and 32bit wide interconnection scheme based on the AHB protocol.
Enables parallel routing, up to four paths, between 4 masters and 4 slave ports.
Video Interface 
Supports two 12-bit , 640x480 color image resolution video streams
12-bit Glue less interface to high dynamic Range Image sensor
Color Bayer De-mosaic support
12 bit to 8 bit Pixel compression with high configurable Gama curve approximation.
Memory support:
EyeQ™ supports several off-chip and on-chip memory units:
On chip 288KByte 64 bit data width fast memory-slave port #2
On chip 4KByte for bootstrap code-Slave Port #0
32 bit external SDRAM controller-Slave port #1
16 bit external Flash and SRAM controller-Slave Port #0
Other peripherals: 
Vector Interrupt Controller:
Supports 32 interrupt sources
Supports 16 interrupt vectors
Serial Interfaces:
UART controller
2 x CAN controller
I2C Controller
Power On Reset

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